1. Field of the Invention
The present invention generally relates to the manufacture of very large scale integrated (VLSI) circuit devices and, more particularly, to the fidelity enhancement of lithographic and reactive ion etched (RIE) images through the use of optical proximity correction (OPC).
2. Background Description
Manufacturing of semiconductor devices is dependent upon the accurate replication of computer aided design (CAD) generated patterns onto the surface of a device substrate. The replication process is typically performed using optical lithography followed by a variety of subtractive (etch) and additive (deposition) processes. Optical lithography patterning involves the illumination of a metallic coated quartz plate known as a photomask which contains a magnified image of the computer generated pattern etched into the metallic layer. This illuminated image is reduced in size and patterned into a photosensitive film on the device substrate. As a result of the interference and processing effects which occur during pattern transfer, images formed on the device substrate deviate from their ideal dimensions and shape as represented by the computer images. These deviations depend on the characteristics of the patterns as well as a variety of process conditions. Because these deviations can significantly effect the performance of the semiconductor device, many approaches have been pursued which focus on CAD compensation schemes which ensure a resultant ideal image.
The performance enhancement of advanced VLSI circuitry (that is, the speed enhancement versus dimension reduction of the circuits) is increasingly limited by the lack of pattern fidelity in a series of lithography and RIE processes at small dimensions (e.g., sub 0.5 .mu.m). In the photolithography process, a pattern is transferred from a photomask to a photosensitive film (resist) on the wafer. In the RIE process, this pattern in the resist is transferred into a variety of films on the wafer substrate.
An alternative to the costly development of processes with every higher effective resolution is the selective biasing of mask patterns to compensate for the pattern distortions occurring during wafer processing. The term Optical Proximity Correction (OPC) is commonly used to describe this process of selective mask biasing, even though the trend exists to include pattern distortions unrelated to the optical image transfer. The idea of biasing patterns to compensate for image transfer infidelities has been commonly applied to E-beam lithography to counteract the effects of back scattered electrons, both in the writing of photo masks and in direct wafer writing operations. See for example U.S. Pat. No. 5,278,421.
OPC extends the use of the automatic pattern biasing concept to the two major pattern transfer processes used in VLSI technologies. Current implementations of OPC can be categorized as "rules-based" in which patterns are sorted and biased in the computer aided design (CAD) data set based on rules relating bias amounts to pattern attributes such as size, proximity, and density, and "convolution-based" in which CAD patterns are biased based on particular pattern environment. Both the rules and convolution functions can be generated either from process simulations or empirical data. For examples of "rules-based" OPC implementations, see Richard C. Henderson and Oberdan W. Otto, "CD data requirements for proximity effect corrections", 14th Annual BACUS Symposium on Photomask Technology and Management, William L. Brodsky and Gilbert V. Shelden, Editors, Proc. SPIE 2322 (1994), pp. 218-228, and Oberdan W. Otto, Joseph G. Garofalo, K. K. Low, Chi-Min Yuan, Richard C. Henderson, Christophe Pierrat, Robert L. Kostelak, Shiela Vaidya, and P. K. Vasudev, "Automated optical proximity correction--a rules-based approach", Optical/Laser Microlithography VII, Timothy A. Brunner, Editor, Proc. SPIE 2197 (1994), pp. 278-293. For examples of the "convolution-based" OPC implementations, see John P. Stirniman and Michael L. Rieger, "Fast proximity correlation with zone sampling", Optical/Laser Microlithography VII, Timothy A. Brunner, Editor, Proc. SPIE 2197 (1994), pp. 294-301, and John Stirniman and Michael Rieger, "Optimnizing proiximity correction for wafer fabrication processes", 14th Annual BACUS Symposium on Photomask Technology and Management, William L. Brodsky and Gilbert V. Shelden, Editors, Proc. SPIE 2322 (1994), pp. 239-246. The common characteristic of these implementations that is most relevant to the present invention is that CAD data are treated as a collection of geometric shapes, rather than designs defining device functionality.
There are two major drawbacks with the current implementations. The first is that using the accuracy of the pattern replication of either the lithography or RIE processes as a success criterion for the OPC, rather than the improvement of device functionality, drives a lot of unnecessary biasing. This increases the cost of the OPC process by complicating the CAD data sets and design rule checking decks and by increasing the CAD, mask writer, and inspection tool data volumes without adding any value to the VLSI chip. This is true for one-dimensional compensations focusing on the correction of line widths, as well as two-dimensional corrections dealing with phenomena such as corner rounding. The second problem relates to the addition of new vertices (jogs and corners) in the CAD layout which significantly increases the data volume and complicates mask inspection. The goal of an efficient OPC routine has to be the minimization of vertices added in the biasing process.